1N4007 Datasheet, PDF (180/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.24.3.6 SPI Mode Boot Parameter Table
Byte Offset
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Table 6-87. 2.5.3.7 SPI Mode Boot Parameter Table
Name
options
Address Width
NPin
Chipsel
Mode
C2T Delay
CPU Freq MHz
Bus Freq, MHz
Bus Freq, kHz
Read Addr MSW
Read Addr LSW
Next chipsel
Next read MSW
Next read LSW
Description
See Figure 6-44
The number of bytes in the SPI device address. Can be 2 or 3 (16 or 24 bit)
The operational mode, 4 or 5 pin
The chip select used. Can be 0-3.
SPI mode, 0-3
SPI chip select active to transmit start delay value (0-255)
The speed of the CPU, in MHz
The MHz portion of the SPI bus frequency. Default = 5MHz
The kHz portion of the SPI buf frequency. Default = 0
The first address to read from, MSW (valid for 24 bit address width only)
The first address to read from, LSW
Chipsel value used after boot config table processing is complete
The next read address, MSW after config table processing is complete
The next read address, LSW after config table processing is complete
The bus frequency programmed into the SPI by the boot ROM is from the table: MHz.kHz. So for a 5.1
MHz bus frequency the MHz value is 5, the kHz value is 100.
Figure 6-44. SPI Options Field Bit Map
15
Reserved
2
1
0
Mode
Parameter
Mode
Value
0
1
2
3
Table 6-88. SPI Options Field Description
Description
Load a boot parameter table from the SPI
Load boot records from the SPI (boot tables)
Load boot config records from the SPI (boot config tables)
Reserved
180 Detailed Description
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