1N4007 Datasheet, PDF (65/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
5.7.16 uPP Timing and Switching
Table 5-25. uPP Timing Requirements
(See Figure 5-27, Figure 5-28, Figure 5-29, Figure 5-30.)
NO.
MIN MAX UNIT
1 t_c(INCLK)
Cycle time, CHn_CLK
SDR mode
13.33
ns
DDR mode
26.66
2 t_w(INCLKH)
Pulse width, CHn_CLK high
SDR mode
DDR mode
5
ns
10
3 t_w(INCLKL)
Pulse width, CHn_CLK low
SDR mode
DDR mode
5
ns
10
4 t_{su(STV-INCLKH)}
5 t_{h(INCLKH-STV)}
6 t_{su(ENV-INCLKH)}
7 t_{h(INCLKH-ENV)}
8 t_{su(DV-INCLKH)}
9 t_h(INCLKH-DV)
10 t_{su(DV-INCLKL)}
11 t_h(INCLKL-DV)
19 t_{su(WTV-OUTCLKL)}
20 t_{h(INCLKL-WTV)}
21 t_c(2xTXCLK)
Setup time, CHn_START valid before CHn_CLK high
Hold time, CHn_START valid after CHn_CLK high
Setup time, CHn_ENABLE valid before CHn_CLK high
Hold time, CHn_ENABLE valid after CHn_CLK high
Setup time, CHn_DATA/XDATA valid before CHn_CLK high
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
Setup time, CHn_DATA/XDATA valid before CHn_CLK low
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
Setup time, CHn_WAIT valid before CHn_CLK high
Hold time, CHn_WAIT valid after CHn_CLK high
Cycle time, 2xTXCLK input clock⁽¹⁾
4
ns
0.8
ns
4
ns
0.8
ns
4
ns
0.8
ns
4
ns
0.8
ns
4
ns
0.8
ns
6.66
ns
(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 5-26. uPP Switching Characteristics
(See Figure 5-29 and Figure 5-30.)
NO.
PARAMETER
12 t_c(OUTCLK)
Cycle time, CHn_CLK
SDR mode
DDR mode
13 t_w(OUTCLKH)
Pulse width, CHn_CLK high
SDR mode
DDR mode
14 t_w(OUTCLKL)
Pulse width, CHn_CLK low
SDR mode
DDR mode
15 t_{d(OUTCLKH-STV)} Delay time, CHn_START valid after CHn_CLK high
16 t_{d(OUTCLKH-ENV)} Delay time, CHn_ENABLE valid after CHn_CLK high
17 t_{d(OUTCLKH-DV)} Delay time, CHn_DATA/XDATA valid after CHn_CLK high
18 t_{d(OUTCLKL-DV)} Delay time, CHn_DATA/XDATA valid after CHn_CLK low
MIN
13.33
26.66
5
10
5
10
1
1
1
1
MAX UNIT
ns
ns
ns
11 ns
11 ns
11 ns
11 ns
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Specifications
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