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1N4007 Datasheet, PDF (155/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A
www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.20.2 Trace
The C6654 and C6652 devices support trace. Trace is a debug technology that provides a detailed,
historical account of application code execution, timing, and data accesses. Trace collects, compresses,
and exports debug information for analysis. Trace works in real-time and does not impact the execution of
the system.
For more information on board design guidelines for trace advanced emulation, see the 60-Pin Emulation
Header Technical Reference.
6.20.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan
supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (for example, no
EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test
Specification (IEEE1149.1), while all of the SerDes (SGMII) support the AC-coupled net test defined in
AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain
fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant
with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
Specification (EAI/JESD8-5).
6.20.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6654 and C6652 DSP includes an internal pulldown (IPD) on the TRST pin
to ensure that TRST will always be asserted upon power up and the internal emulation logic of the DSP
will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments
actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect
the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to
initialize the DSP after power up and externally drive TRST high before attempting any emulation or
boundary scan operations.
6.21 DSP Core Description
The C66x DSP extends the performance of the C64x+ and C674x DSPs through enhancements and new
features. Many of the new features target increased performance for vector processing. The C64x+ and
C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On
the C66x DSP, the vector processing capability is improved by extending the width of the SIMD
instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. For example the
QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four
32-bit data each. The C66x DSP also supports SIMD for floating-point operations. Improved vector
processing capability (each instruction can process multiple data in parallel) combined with the natural
instruction level parallelism of C6000 architecture (for example, execution of up to 8 instructions per cycle)
results in a very high level of parallelism that can be exploited by DSP programmers through the use of
TI's optimized C/C++ compiler.
The C66x DSP consists of eight functional units, two register files, and two data paths as shown in
Figure 6-25. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of
64 registers. The general-purpose registers can be used for data or can be data address pointers. The
data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit
data. Multiplies also support 128-bit data. 40-bit-long or 64-bit-long values are stored in register pairs, with
the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register
(which is always an odd-numbered register). 128-bit data values are stored in register quadruplets, with
the 32 LSBs of data placed in a register that is a multiple of 4 and the remaining 96 MSBs in the next 3
upper registers.
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