1N4007 Datasheet, PDF (127/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
Table 6-36 shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to
determine allowed connections between masters and slaves. Unlike privilege IDs, which can be shared
across different masters, master IDs are unique to each master.
Table 6-36. Master ID Settings⁽¹⁾
MASTER ID
MASTER
MASTER ID
MASTER
0
CorePac0
40 - 47
Reserved
1
Reserved
48
DAP
2
Reserved
49
Reserved
3
Reserved
50
EDMA3_CC
4
Reserved
51
Reserved
5
Reserved
52
MSMC ⁽²⁾
6
Reserved
53
PCIe (C6654 Only)
7
Reserved
54
Reserved
8
CorePac0_CFG
55
Reserved
9
Reserved
56
EMAC (C6654 Only)
10
Reserved
57 - 87
Reserved
11
Reserved
88 - 91
QM_PKTDMA
12
Reserved
92 - 93
QM_Second
13
Reserved
94
Reserved
14
Reserved
95
uPP
15
Reserved
96 - 127
Reserved
16
Reserved
128
Tracer_core_0 ⁽³⁾
17
Reserved
129
Reserved
18
Reserved
130
Reserved
19
Reserved
131
Reserved
20
Reserved
132
Reserved
21
Reserved
133
Reserved
22
Reserved
134
Reserved
23
Reserved
135
Reserved
24
Reserved
136
Reserved
25
Reserved
137
Reserved
26
Reserved
138
Reserved
27
Reserved
139
Reserved
28
EDMA_TC0 read
140
Tracer_DDR
29
EDMA_TC0 write
141
Tracer_SEM
30
EDMA_TC1 read
142
Tracer_QM_CFG
31
EDMA_TC1 write
143
Tracer_QM_DMA
32
EDMA_TC2 read
144
Tracer_CFG
33
EDMA_TC2 write
145
Reserved
34
EDMA_TC3 read
146
Reserved
35
EDMA_TC3 write
147
Reserved
36 - 37
Reserved
148
Tracer_EMIF16
38 - 39
Reserved
(1) Some of the PKTDMA-based peripherals require multiple master IDs. QMS_PKTDMA is assigned with 88,89,90,91, but only 88-89 are
actually used. There are two master ID values are assigned for the QM_second master port, one master ID for external linking RAM and
the other one for the PDSP/MCDM accesses.
(2) The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.
(3) All Tracers are set to the same master ID and bit 7 of the master ID must be 1.
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Detailed Description 127