1N4007 Datasheet, PDF (188/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac
interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return 0, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error
status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the
C66x CorePac User's Guide.
7.3 Bandwidth Management
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting
access to the highest priority requestor. The following four resources are managed by the Bandwidth
Management control hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
The priority level for operations initiated within the C66x CorePac are declared through registers in the
C66x CorePac. These operations are:
• DSP-initiated transfers
• User-programmed cache coherency operations
• IDMA-initiated transfers
The priority level for operations initiated outside the C66x CorePac by system peripherals is declared
through the Priority Allocation Register (PRI_ALLOC), see Section 9.4 for more details. System
peripherals with no fields in the PRI_ALLOC have their own registers to program their priorities.
More information on the bandwidth management features of the C66x CorePac can be found in the C66x
CorePac User's Guide.
7.4 Power-Down Control
The C66x CorePac supports the ability to power down various parts of the C66x CorePac. The power
down controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware,
the DSP, and the entire C66x CorePac. These power-down features can be used to design systems for
lower overall system power requirements.
NOTE
The C6654 and C6652 do not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the C66x CorePac
User's Guide.
188 C66x CorePac
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