1N4007 Datasheet, PDF (107/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
Table 6-26 shows the mapping of system events. For more information on the Interrupt Controller, see the
C66x CorePac User's Guide.
Table 6-26. C6654 and C6652 System Event Inputs — C66x CorePac Primary Interrupts
INPUT EVENT
NUMBER
0
1
2
3
4
5
6
7
8
9
INTERRUPT EVENT
EVT0
EVT1
EVT2
EVT3
TETBHFULLINTn ⁽¹⁾
TETBFULLINTn ⁽¹⁾
TETBACQINTn ⁽¹⁾
TETBOVFLINTn ⁽¹⁾
TETBUNFLINTn ⁽¹⁾
EMU_DTDMA
10
MSMC_mpf_errorn ⁽²⁾
11
EMU_RTDXRX
12
EMU_RTDXTX
13
IDMA0
14
IDMA1
15
SEMERRn ⁽³⁾
16
SEMINTn ⁽³⁾
17
PCIExpress_MSI_INTn ⁽⁴⁾
18
PCIExpress_MSI_INTn+4 ⁽⁴⁾
19
MACINTn ⁽⁵⁾
20
Reserved
21
Reserved
22
CIC0_OUT(0+20*n) ⁽⁶⁾
23
CIC0_OUT(1+20*n) ⁽⁶⁾
24
CIC0_OUT(2+20*n) ⁽⁶⁾
25
CIC0_OUT(3+20*n) ⁽⁶⁾
26
CIC0_OUT(4+20*n) ⁽⁶⁾
27
CIC0_OUT(5+20*n) ⁽⁶⁾
28
CIC0_OUT(6+20*n) ⁽⁶⁾
29
CIC0_OUT(7+20*n) ⁽⁶⁾
30
CIC0_OUT(8+20*n) ⁽⁶⁾
31
CIC0_OUT(9+20*n) ⁽⁶⁾
32
QM_INT_LOW_0
33
QM_INT_LOW_1
34
QM_INT_LOW_2
35
QM_INT_LOW_3
36
QM_INT_LOW_4
DESCRIPTION
Event combiner 0 output
Event combiner 1 output
Event combiner 2 output
Event combiner 3 output
TETB is half full
TETB is full
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
ECM interrupt for:
• 1. Host scan access
• 2. DTDMA transfer complete
• 3. AET interrupt
Memory protection fault indicators for local core
RTDX receive complete
RTDX transmit complete
IDMA channel 0 interrupt
IDMA channel 1 interrupt
Semaphore error interrupt
Semaphore interrupt
Message signaled interrupt mode (C6654 Only)
Message signaled interrupt mode (C6654 Only)
EMAC interrupt (C6654 Only)
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
QM Interrupt for 0~31 Queues
QM Interrupt for 32~63 Queues
QM Interrupt for 64~95 Queues
QM Interrupt for 96~127 Queues
QM Interrupt for 128~159 Queues
(1) CorePac[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn.
(2) CorePac[n] will receive MSMC_mpf_errorn.
(3) CorePac[n] will receive SEMINTn and SEMERRn.
(4) CorePac[n] will receive PCIEXpress_MSI_INTn.
(5) CorePac[n] will receive MACINTn/MACRXINTn/MACTXINTn/MACTRESHn.
(6) n is core number.
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Detailed Description 107