1N4007 Datasheet, PDF (83/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.5.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following:
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their
normal operating conditions. A RESETFULL pin is also provided to allow the onboard host to reset the
entire device including the reset isolated logic. The assumption is that the device is already powered up
and hence, unlike the POR pin, the RESETFULL pin will be driven by the onboard host control instead of
the power-good circuitry. For power-on reset, the Main PLL Controller comes up in bypass mode and the
PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After
the POR pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set
to their reset state and will remain at their reset state until otherwise configured by their respective
peripheral. All peripherals that are power managed, are disabled after a power-on reset and must be
enabled through the Device State Control Registers (for more details, see Table 8-2).
2. Clocks are reset, and they are propagated throughout the device to reset any logic that was using
reset synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the
device is in reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional time
for the chip-level PLLs to lock.
4. The POR pin can now be deasserted. Reset-sampled pin values are latched at this point. The chip
level PLLs are taken out of reset and begin their locking sequence, and all power-on device
initialization also begins.
5. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time, the
DDR3 PLL has already completed its locking sequence and is outputting a valid clock. The system
clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles
of their respective system reference clocks. After the pause, the system clocks are restarted at their
default divide by settings.
6. The device is now out of reset and device execution begins as dictated by the selected boot mode.
NOTE
To most of the device, reset is deasserted only when the POR and RESET pins are both
deasserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The
RESET pin should not be tied together with the POR pin.
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Detailed Description
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