1N4007 Datasheet, PDF (46/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
Table 5-4. Boot Configuration Timing Requirements⁽¹⁾
(See Figure 5-4.)
NO.
MIN
1
tsu(GPIOn-RESETFULL) Setup time - GPIO valid before RESETFULL asserted
12C
2
th(RESETFULL-GPIOn) Hold time - GPIO valid after RESETFULL asserted
12C
(1) C = 1/SYSCLK1 frequency in ns.
POR
1
RESETFULL
www.ti.com
MAX
UNIT
ns
ns
GPIO[15:0]
2
Figure 5-4. Boot Configuration Timing
5.7.3 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device power up. The PLL should not be operated until this stabilization time has
elapsed.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
Main PLL reset time value, see Table 5-5.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main
PLL lock time is given in Table 5-5.
Table 5-5. Main PLL Stabilization, Lock, and Reset Times
PLL stabilization time
PLL lock time
PLL reset time
(1) PLLD is the value in PLLD bit fields of MAINPLLCTL0 register
(2) C = SYSCLK1(N|P) cycle time in ns.
MIN
TYP
100
1000
MAX
500 ×(PLLD⁽¹⁾+1) × C⁽²⁾
UNIT
µs
ns
46
Specifications
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654