1N4007 Datasheet, PDF (198/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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8.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the
Bootcfg MMR values. When the kicker is locked (which it is initially after power on reset), none of the
Bootcfg MMRs are writable (they are only readable). On the C6654 and C6652, the exceptions to this are
the IPC registers such as IPCGRx and IPCARx. These registers are not protected by the kicker
mechanism. This mechanism requires two MMR writes to the KICK0 and KICK1 registers with exact data
values before the kicker lock mechanism is unlocked. See Table 8-2 for the address location. Once
released, then all the Bootcfg MMRs having write permissions are writable (the read only MMRs are still
read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other
data value to either of these kick MMRs will lock the kicker mechanism and block any writes to Bootcfg
MMRs. To ensure protection of all Bootcfg MMRs, software must always relock the kicker mechanism
after completing the MMR writes.
8.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI
based on CORESEL. The LRESETNMI PIN Status Register is shown in Figure 8-4 and described in
Table 8-6.
Figure 8-4. LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
18
Reserved
R, +0000 0000
Legend: R = Read only; -n = value after reset;
17
16
15
2
Reserved
NMI0
Reserved
R-0
WC,+0
R, +0000 0000
1
Reserved
WC,+0
0
LR0
WC,+0
Table 8-6. LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
BIT
31-18
17
16
15-2
1
0
FIELD
Reserved
Reserved
NMI0
Reserved
Reserved
LR0
DESCRIPTION
Reserved
Reserved
CorePac0 in NMI
Reserved
Reserved
CorePac0 in Local Reset
198 Device Configuration
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