1N4007 Datasheet, PDF (77/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.3.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of
many of the clocks is contingent on the state of the boot configuration pins. Table 6-4 describes the clock
sequencing and the conditions that affect the clock operation. All clock drivers should be in a high-
impedance state until CVDD is at a valid level and that all clock inputs either be active or in a static state
with one leg pulled low and the other connected to CVDD.
Table 6-4. Clock Sequencing
CLOCK
DDRCLK
CORECLK
PCIECLK
(C6654 only)
CONDITION
SEQUENCING
None
Must be present 16 µs before POR transitions high.
None
CORECLK used to clock the core PLL. It must be present 16 µs before POR transitions high.
PCIE will be used as a boot PCIECLK must be present 16 µs before POR transitions high.
device.
PCIE will be used after
boot.
PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE
is removed from reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
6.3.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to
prevent a large amount of static current and to prevent overstress of the device. A power-good circuit that
monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure
occurs on any voltage rail, POR should transition to low to prevent overcurrent conditions that could
possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails.
Long-term exposure to an environment in which one of the power supply voltages is no longer present will
affect the reliability of the device. Holding the device in reset is not an acceptable solution because
prolonged periods of time with an active reset can also affect long term reliability.
6.3.3 Power Supply Decoupling and Bulk Capacitors
To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors
are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and
decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on
selection of Power Supply Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone
Devices.
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