1N4007 Datasheet, PDF (212/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
8.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0. This
register islocated in Bootcfg memory space. The Reset Mux Register is shown in Figure 8-17 and
described in Table 8-19.
Figure 8-17. Reset Mux Register RSTMUXx
31
10
9
8
7
5
4
Reserved
EVTSTATCLR Reserved
DELAY
EVTSTAT
R, +0000 0000 0000 0000 0000
00
RC, +0
R, +0
RW, +100
R, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
3
1
OMODE
RW, +000
0
LOCK
RW, +0
BIT
31-10
9
FIELD
Reserved
EVTSTATCLR
8
Reserved
7-5 DELAY
4
EVTSTAT
3-1 OMODE
0
LOCK
Table 8-19. Reset Mux Register Field Descriptions
DESCRIPTION
Reserved
Clear event status
• 0 = Writing 0 has no effect
• 1 = Writing 1 clears the EVTSTAT bit
Reserved
Delay cycles between NMI and local reset
• 000b = 256 CPU/6 cycles delay between NMI and local reset, when OMODE = 100b
• 001b = 512 CPU/6 cycles delay between NMI and local reset, when OMODE=100b
• 010b = 1024 CPU/6 cycles delay between NMI and local reset, when OMODE=100b
• 011b = 2048 CPU/6 cycles delay between NMI and local reset, when OMODE=100b
• 100b = 4096 CPU/6 cycles delay between NMI and local reset, when OMODE=100b (Default)
• 101b = 8192 CPU/6 cycles delay between NMI and local reset, when OMODE=100b
• 110b = 16384 CPU/6 cycles delay between NMI and local reset, when OMODE=100b
• 111b = 32768 CPU/6 cycles delay between NMI and local reset, when OMODE=100b
Event status.
• 0 = No event received (Default)
• 1 = WD timer event received by Reset Mux block
Timer event operation mode
• 000b = WD timer event input to the reset mux block does not cause any output event (default)
• 001b = Reserved
• 010b = WD timer event input to the reset mux block causes local reset input to CorePac
• 011b = WD timer event input to the reset mux block causes NMI input to CorePac
• 100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to
CorePac. Delay between NMI and local reset is set in DELAY bit field.
• 101b = WD timer event input to the reset mux block causes device reset to C6654 and C6652
• 110b = Reserved
• 111b = Reserved
Lock register fields
• 0 = Register fields are not locked (default)
• 1 = Register fields are locked until the next timer reset
212 Device Configuration
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