1N4007 Datasheet, PDF (69/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
5.7.18 JTAG Electrical Data/Timing
Table 5-29. JTAG Test Port Timing Requirements
(See Figure 5-32.)
NO.
MIN
1
t_c(TCK)
1a tw(TCKH)
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
34
13.6
1b tw(TCKL)
Pulse duration, TCK low(40% of tc)
13.6
3 tsu(TDI-TCK) input setup time, TDI valid to TCK high
3.4
3 tsu(TMS-TCK) input setup time, TMS valid to TCK high
3.4
4 th(TCK-TDI)
input hold time, TDI valid from TCK high
17
4 th(TCK-TMS) input hold time, TMS valid from TCK high
17
Table 5-30. JTAG Test Port Switching Characteristics⁽¹⁾
(See Figure 5-32.)
NO.
PARAMETER
MIN
2
t_d(TCKL-TDOV)
Delay time, TCK low to TDO valid
(1) Over recommended operating conditions.
TCK
TDO
3
TDI / TMS
1
1a
1b
2
4
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
MAX UNIT
13.6 ns
Figure 5-32. JTAG Test-Port Timing
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Specifications
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