1N4007 Datasheet, PDF (50/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
5.7.8 I²C Electrical Data/Timing
5.7.8.1 Inter-Integrated Circuits (I²C) Timing
Table 5-9. I²C Timing Requirements⁽¹⁾
(See Figure 5-9.)
STANDARD MODE
FAST MODE
NO.
MIN
MAX
MIN MAX UNIT
1
t_c(SCL)
Cycle time, SCL
10
2
t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated Start
condition)
4.7
2.5
µs
0.6
µs
3
t_h(SDAL-SCLL)
Hold time, SCL low after SDA low (for a Start and a
repeated Start condition)
4
0.6
µs
4
t_w(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
t_w(SCLH)
Pulse duration, SCL high
6
t_{su(SDAV-SCLH)} Setup time, SDA valid before SCL high
7
t_h(SCLL-SDAV) Hold time, SDA valid after SCL low (for I²C bus devices)
4
250
0 ⁽³⁾
3.45
0.6
100 ⁽²⁾
0 ⁽³⁾
µs
ns
0.9⁽⁴⁾ µs
8
t_w(SDAH)
Pulse duration, SDA high between Stop and Start
conditions
4.7
1.3
µs
9
t_r(SDA)
10
t_r(SCL)
11
t_f(SDA)
12
t_f(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1C_b(5)
1000 20 + 0.1C_b(5)
300 20 + 0.1C_b(5)
300 20 + 0.1C_b(5)
300 ns
300 ns
300 ns
300 ns
13 t_{su(SCLH-SDAH)} Setup time, SCL high before SDA high (for Stop condition)
4
0.6
µs
14 t_w(SP)
15
C_b ⁽⁵⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50 ns
400
400 pF
(1) The I²C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down
(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus™ system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
SDA
8
SCL
4
10
1
3
6
5
12
7
3
2
9
14
13
Stop Start
Repeated
Start
Stop
Figure 5-9. I²C Receive Timings
50
Specifications
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