1N4007 Datasheet, PDF (179/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.24.3.5 I2C Mode Boot Parameter Table
Byte Offset
12
14
16
18
20
22
24
26
28
30
Table 6-85. I2C Mode Boot Parameter Table
Name
Options
Boot Dev Addr
Boot Dev Addr Ext
Broadcast Addr
Local Address
Device Freq
Bus Frequency
Next Dev Addr
Next Dev Addr Ext
Address Delay
Description
See Figure 6-43
The I2C device address to boot from
Extended boot device address, or I2C bus address (typically 0x50, 0x51)
In master broadcast boot, this is the I2C address to send the boot data to
The I2C address of this device.
The operating frequency of the device (MHz). Used to compute the divide down to
the I2C module
The desired I2C data rate (kHz).
The next device to boot from (used in boot config mode)
The extended next boot device address
The number of CPU cycles to delay between writing the address to an I2C
EEPROM and reading data. This allows the I2C EEPROM time to load the data.
Figure 6-43. I2C Mode Boot Options Bitfield
15
Reserved
2
1
0
Mode
Parameter
Mode
Value
0
1
2
3
Table 6-86. Register Description
Description
Load a boot parameter table from the I2C
Load boot records from the I2C (boot tables)
Load boot config records from the I2C (boot config tables)
Perform a slave mode boot, listening on the local address specified in the table.
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Detailed Description 179