1N4007 Datasheet, PDF (207/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
8.3.14 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is
the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register
appears on device pin HOUT.
The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles
(CPU/6) followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6
cycle pulse blocking window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they
are beyond 8 CPU/6 cycle period. The IPC Generation Host Register is shown in Figure 8-13 and
described in Table 8-15.
Figure 8-13. IPC Generation Registers (IPCGRH)
31
30
29
28
27
8
SRCS SRCS SRCS SRCS
27
26
25
24
SRCS23 – SRCS4
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
7
6
5
4
SRCS3 SRCS2 SRCS1 SRCS0
RW +0 RW +0 RW +0 RW +0
3
1
Reserved
R, +000
0
IPCG
RW +0
BIT
31-4
FIELD
SRCSx
3-1 Reserved
0
IPCG
Table 8-15. IPC Generation Registers (IPCGRH) Field Descriptions
DESCRIPTION
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Host interrupt generation.
Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Device Configuration 207