1N4007 Datasheet, PDF (146/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
Table 6-52. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
02C0 8150
02C0 8154
02C0 8158
02C0 815C
02C0 8160
02C0 8164
02C0 8168
02C0 816C
02C0 8170
02C0 8174
02C0 81D0
02C0 81D4
02C0 81D8
02C0 81DC
02C0 81E0
02C0 81E4
02C0 81E8
02C0 81EC
02C0 8200 - 02C0 82FC
02C0 8300 - 02C0 84FC
02C0 8500
02C0 8504
02C0 8508
02C0 850C - 02C0 85FC
02C0 8600
02C0 8604
02C0 8608
02C0 860C
02C0 8610
02C0 8614
02C0 8618
02C0 861C
02C0 8620
02C0 8624
02C0 8628
02C0 862C
02C0 8630
02C0 8634
02C0 8638
02C0 863C
02C0 8640
02C0 8644
02C0 8648
02C0 864C
02C0 8650
02C0 8654
02C0 8658
ACRONYM
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
-
-
MACADDRLO
MACADDRHI
MACINDEX
-
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
TX1CP
TX2CP
TX3CP
TX4CP
TX5CP
TX6CP
REGISTER NAME
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register
MAC Configuration Register
Soft Reset Register
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
Transmit Pause Timer Register
See Table 6-53.
Reserved
MAC Address Low Bytes Register (used in Receive Address Matching)
MAC Address High Bytes Register (used in Receive Address Matching)
MAC Index Register
Reserved
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive t Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive t Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive t Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive t Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register
146 Detailed Description
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