1N4007 Datasheet, PDF (162/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
Table 6-60. Memory Map Summary (continued)
LOGICAL 32-BIT ADDRESS
PHYSICAL 36-BIT
ADDRESS
START
END
START
END
70000000 73FFFFFF 0 70000000 0 73FFFFFF
BYTES
64M
74000000 77FFFFFF 0 74000000 0 77FFFFFF 64M
78000000 7BFFFFFF 0 78000000 0 7BFFFFFF 64M
7C000000 7FFFFFFF 0 7C000000 0 7FFFFFFF 64M
80000000 FFFFFFFF 8 00000000 8 7FFFFFFF 2G
DESCRIPTION
EMIF16 CE0 data space, supports NAND, NOR, or SRAM
memory ⁽¹⁾
EMIF16 CE1 data space, supports NAND, NOR, or SRAM
memory ⁽¹⁾
EMIF16 CE2 data space, supports NAND, NOR, or SRAM
memory ⁽¹⁾
EMIF16 CE3 data space, supports NAND, NOR or SRAM
memory ⁽¹⁾
DDR3 EMIF data⁽²⁾
(1) 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. The 32MB and 16MB size restrictions
do not apply to NAND.
(2) The memory map only shows the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access
(up to 8GB), see the MPAX configuration details in C66x CorePac User's Guide and Multicore Shared Memory Controller (MSMC) for
KeyStone Devices User's Guide in Section 10.3.
6.23 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is
started automatically after each power-on reset, warm reset, and system reset. A local reset to an
individual C66x CorePac should not affect the state of the hardware boot controller on the device. For
more details on the initiators of the resets, see Section 6.5. The bootloader uses a section of the L2
SRAM (start address 0x008EFD00 and end address 0x008F FFFF) during initial booting of the device. For
more details on the type of configurations stored in this reserved L2 section see the Bootloader for the
C66x DSP User's Guide.
162 Detailed Description
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