1N4007 Datasheet, PDF (191/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
8.2 Peripheral Selection After Device Reset
Several of the peripherals on the C6654 and C6652 are controlled by the Power Sleep Controller (PSC).
By default, the PCIe is held in reset and clock-gated. The memory in this module is also in a low-leakage
sleep mode. Software is required to turn this memory on. The software enables the module (turns on
clocks and deasserts reset) before this module can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically
enable the module.
All other modules come up enabled by default and there is no special software sequence to enable. For
more detailed information on the PSC use, see the Power Sleep Controller (PSC) for KeyStone Devices
User's Guide.
8.3 Device State Control Registers
The C6654 and C6652 devices has a set of registers that are used to provide the status or configure
certain parts of its peripherals. Table 8-2 lists these registers.
ADDRESS
START
0x02620000
0x02620008
0x02620018
0x0262001C
0x02620020
0x02620024
0x02620038
0x0262003C
0x02620040
0x02620044
0x02620048
0x0262004C
0x02620050
0x02620054
0x02620058
0x0262005C
0x02620060
0x026200E0
0x02620110
0x02620118
0x02620130
0x02620134
0x02620138
0x0262013C
0x02620140
0x02620144
0x02620148
0x0262014C
0x02620150
0x02620154
Table 8-2. Device State Control Registers
ADDRESS END SIZE
0x02620007
8B
0x02620017
16B
0x0262001B 4B
0x0262001F 4B
0x02620023
4B
0x02620037
20B
0x0262003B 4B
0x0262003F 4B
0x02620043
4B
0x02620047
4B
0x0262004B 4B
0x0262004F 4B
0x02620053
4B
0x02620057
4B
0x0262005B 4B
0x0262005F 4B
0x026200DF 128B
0x0262010F 48B
0x02620117
8B
0x0262012F 24B
0x02620133
4B
0x02620137
4B
0x0262013B 4B
0x0262013F 4B
0x02620143
4B
0x02620147
4B
0x0262014B 4B
0x0262014F 4B
0x02620153
4B
0x02620157
4B
FIELD
Reserved
Reserved
JTAGID
Reserved
DEVSTAT
Reserved
KICK0
KICK1
DSP_BOOT_ADDR0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MACID
Reserved
LRSTNMIPINSTAT_CLR
RESET_STAT_CLR
Reserved
BOOTCOMPLETE
Reserved
RESET_STAT
LRSTNMIPINSTAT
DEVCFG
PWRSTATECTL
Reserved
DESCRIPTION
See Section 8.3.3.
See Section 8.3.1.
See Section 8.3.4.
The boot address for C66x DSP CorePac0
Reserved
See Section 6.14.
See Section 8.3.6.
See Section 8.3.8.
See Section 8.3.9.
See Section 8.3.7.
See Section 8.3.5.
See Section 8.3.2.
See Section 8.3.10.
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Device Configuration 191