1N4007 Datasheet, PDF (225/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
Bridge_4
From TeraNet_3P_B
TeraNet
6P_B
CPU/6
Figure 9-5. TeraNet 6P_B
S ^SmartReflex
S
GPIO
S
I²C
S ^{UART (´ 2)}
S ^BOOTCFG
S
PSC
S ^PLL_CTL
S ^Debug_SS
S ^{CIC (´ 3)}
S ^{Timer (´ 8)}
S ^MPU4
S ^EMAC
S ^{McBSP ´ 2}
S ^SEC_CTL
S ^SEC_KEY_MGR
S
Efuse
9.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable
priority registers allow software configuration of the data traffic through the TeraNet. A lower number
means higher priority - PRI = 000b = urgent, PRI = 111b = low.
Most master ports provide their priority directly and do not need a default priority setting. Examples include
the CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-
based peripherals also have internal registers to define the priority level of their initiated transactions.
Some masters do not have apriority allocation register of their own. For these masters, a priority allocation
register is provided for them and described Section 9.4.1 and Section 9.4.2. For all other modules, see the
respective User Guides in Section 10.3 for programmable priority registers.
9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
The packet DMA secondary port is one master port that does not have priority allocation register inside
the IP. The priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC
register in Figure 9-6 and Table 9-3.
Figure 9-6. Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
Reserved
R/W-00000000000000000000001000011
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
2
0
PKTDMA_PRI
RW-000
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