1N4007 Datasheet, PDF (170/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.24.2.4 PCI Boot Device Configuration (C6654 Only)
Extra device configuration is provided in the PCI bits in the DEVSTAT register. PCI boot is shown in
Figure 6-33 and described in Table 6-68 and Table 6-69.
Figure 6-33. PCI Device Configuration Fields
9
8
7
6
5
4
3
Ref Clock
BAR Config
Reserved
Bit
Field
9
Ref Clock
8-5
BAR Config
4-3
Reserved
Table 6-68. PCI Device Configuration Field Descriptions
Description
PCIe reference clock configuration
• 0 = 100 MHz
• 1 = 250 MHz
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 6-69.
Reserved
BAR CFG
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
Table 6-69. BAR Config / PCIe Window Sizes
BAR0
PCIe MMRs
BAR1
32
16
16
32
16
16
32
32
64
4
4
4
32-BIT ADDRESS TRANSLATION
BAR2
BAR3
BAR4
32
32
32
16
32
64
32
32
64
32
32
64
16
64
64
32
64
64
32
64
64
32
64
128
64
128
256
128
128
128
128
128
256
128
256
256
BAR5
Clone of
BAR4
64-BIT ADDRESS
TRANSLATION
BAR2/3
BAR4/5
256
512
1024
2048
256
512
1024
2048
170 Detailed Description
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