1N4007 Datasheet, PDF (168/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.24.2.2 Ethernet (SGMII) Boot Device Configuration (C6654 Only)
SGMII boot is shown in Figure 6-31 and described in Table 6-66.
Figure 6-31. Ethernet (SGMII) Device Configuration Fields
9
8
SerDes Clock Mult
7
6
Ext connection
5
4
Device ID
Table 6-66. Ethernet (SGMII) Configuration Field Descriptions
Bit Field
Description
9-8 SerDes Clock Mult SGMII SerDes input clock. The output frequency of the PLL must be 1.25GB.
• 0 = ×8 for input clock of 156.25 MHz
• 1 = ×5 for input clock of 250 MHz
• 2 = ×4 for input clock of 312.5 MHz
• 3 = Reserved
7-6 Ext connection
External connection mode
• 0 = MAC to MAC connection, master with auto negotiation
• 1 = MAC to MAC connection, slave, and MAC to PHY
• 2 = MAC to MAC, forced link
• 3 = MAC to fiber connection
5-3 Device ID
This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.
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