1N4007 Datasheet, PDF (143/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.12.2 I²C Peripheral Register Description(s)
Table 6-51. I²C Registers
HEX ADDRESS RANGE
0253 0000
0253 0004
0253 0008
0253 000C
0253 0010
0253 0014
0253 0018
0253 001C
0253 0020
0253 0024
0253 0028
0253 002C
0253 0030
0253 0034
0253 0038
0253 003C - 0253 007F
REGISTER
ICOAR
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
ICPID1
ICPID2
-
REGISTER NAME
I²C Own Address Register
I²C Interrupt Mask/Status Register
I²C Interrupt Status Register
I²C Clock Low-Time Divider Register
I²C Clock High-Time Divider Register
I²C Data Count Register
I²C Data Receive Register
I²C Slave Address Register
I²C Data Transmit Register
I²C Mode Register
I²C Interrupt Vector Register
I²C Extended Mode Register
I²C Prescaler Register
I²C Peripheral Identification Register 1 [Value: 0x0000 0105]
I²C Peripheral Identification Register 2 [Value: 0x0000 0005]
Reserved
6.13 PCIe Peripheral (C6654 Only)
The 2-lane PCI express (PCIe) module on the device provides an interface between the DSP and other
PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed
data transfer at rates of 5.0 GBaud per lane on the serial links. For more information, see the Peripheral
Component Interconnect Express (PCIe) for KeyStone Devices User's Guide. The PCIe electrical
requirements are fully specified in the PCI Express Base Specification Revision 2.0 of PCI-SIG. TI has
performed the simulation and system characterization to ensure all PCIe interface timings in this solution
are met; therefore, no electrical data/timing information is supplied here for this interface.
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Detailed Description 143