1N4007 Datasheet, PDF (84/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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6.5.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation
modules. POR should also remain deasserted during this time.
Hard reset is initiated by the following:
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog timer
• Emulation
All the above initiators, by default, are configured to act as a hard reset. Except emulation, all the other
three initiators can be configured as soft resets in the RSCFG register in PLLCTL.
The following sequence must be followed during a hard reset:
1. The RESET pin is pulled active low for a minimum of 24 input clock cycles. During this time, the
RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O
are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Configuration
pins are not relatched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high).
NOTE
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise,
if POR is activated (brought low), the minimum POR pulse width must be met. The RESET
pin should not be tied together with the POR pin.
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Detailed Description
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