1N4007 Datasheet, PDF (85/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.5.3 Soft Reset
A soft reset will behave like a hard reset except that the PCIe MMR sticky bits and DDR3 EMIF MMRs
contents are retained. POR should also remain deasserted during this time.
Soft reset is initiated by the following:
• RESET pin
• RSCTRL register in PLLCTL
• Watchdog timer
All the above initiators by default are configured to act as hard reset. Except emulation, all the other three
initiators can be configured as soft resets in the RSCFG register in PLLCTL.
In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected,
and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3
memory controller registers are not reset. In addition, the DDR3 SDRAM memory content is retained if the
user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.
During a soft reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to
propagate through the system. Internal system clocks are not affected. PLLs also remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the
PLL controllers pause their system clocks for about 8 cycles.
– At this point:
– The state of the peripherals before the soft reset is not changed.
– The I/O pins are controlled as dictated by the DEVSTAT register.
– The DDR3 MMRs and PCIe MMR sticky bits retain their previous values. Only the DDR3
Memory Controller and PCIe state machines are reset by the soft reset.
– The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Because the configuration pins are not
latched with a system reset, the previous values, as shown in the DEVSTAT register, are used to select
the boot mode.
6.5.4 Local Reset
The local reset can be used to reset a particular CorePac without resetting any other chip components.
Local reset is initiated by the following (for more details see the Phase-Locked Loop (PLL) for KeyStone
Devices User's Guide:
• LRESET pin
• Based on the setting of the CORESEL[2:0] and RSTCFG register in the PLL controller, one of the
following should be caused by the watchdog timer. See Section 6.6.2.8 and Section 6.9.2:
– Local Reset
– NMI
– NMI followed by a time delay and then a local reset for the CorePac selected
– Hard Reset by requesting reset through PLLCTL
• LPSC MMRs (memory-mapped registers)
6.5.5 Reset Priority
If any of the reset sources in Section 6.5.4 occur simultaneously, the PLLCTL processes only the highest
priority reset request. The reset request priorities are as follows (high to low):
• Power-on reset
• Hard/soft reset
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Detailed Description
85