1N4007 Datasheet, PDF (226/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
Table 9-3. Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
BIT
31-3
2-0
NAME
Reserved
PKTDMA_PRI
DESCRIPTION
Reserved
Control the priority level for the transactions from packet DMA master port, which
access the external linking RAM.
9.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register (C6654 Only)
The EMAC and uPP are master ports that do not have priority allocation registers inside the IP. The
priority level for transaction from these master ports is described by EMAC_UPP_PRI_ALLOC register in
Figure 9-7 and Table 9-4.
Figure 9-7. EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC)
31
27 26
24 23
19 18
16
Reserved
EMAC_EPRI
Reserved
EMAC_PRI
R-00000
RW-110
R-00000
RW-111
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
15
11
Reserved
R-00000
10
8
UPP_EPRI
RW-110
7
3
Reserved
R-00000
2
0
UPP_PRI
RW-111
BIT
31-27
26-24
23-19
18-16
15-11
10-8
7-3
2-0
Table 9-4. EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
NAME
Reserved
EMAC_EPRI
Reserved
EMAC_PRI
Reserved
UPP_EPRI
Reserved
UPP_PRI
DESCRIPTION
Reserved
Control the maximum priority level for the transactions from EMAC master port.
Reserved
Control the priority level for the transactions from EMAC master port.
Reserved
Control the maximum priority level for the transactions from uPP master port.
Reserved
Control the priority level for the transactions from uPP master port.
226 System Interconnect
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654