1N4007 Datasheet, PDF (97/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.6.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, watchdog timer and the RSTCTRL
Register of the PLL controller; that is, a hard reset or a soft reset. By default, these resets will be hard
resets. The Reset Configuration Register (RSTCFG) is shown in Figure 6-11 and described in Table 6-17.
Figure 6-11. Reset Configuration Register (RSTCFG)
31
14
13
12
11
4
3
0
Reserved
PLLCTLRST
TYPE
RESETTYPE
Reserved
WDTYPE[N ⁽¹⁾]
R-0
R/W-0 ⁽²⁾
R/W-0²
R-0
R/W-0²
Legend: R = Read only; R/W = Read/Write; -n = value after reset
(1) Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data
manual).
(2) Writes are conditional based on valid key. For details, see Section 6.6.2.7.
Table 6-17. Reset Configuration Register (RSTCFG) Field Descriptions
BIT
31-14
13
FIELD
Reserved
PLLCTLRSTTYPE
12
RESETTYPE
11-4
3
Reserved
WDTYPE3
2
WDTYPE2
1
WDTYPE1
0
WDTYPE0
DESCRIPTION
Reserved.
PLL controller initiates a software-driven reset of type:
• 0 = Hard reset (default)
• 1 = Soft reset
RESET initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Reserved.
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Detailed Description
97