1N4007 Datasheet, PDF (185/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
7.1.2 L1D Memory
The L1D memory configuration for the C6654 and C6652 devices is as follows:
• 32KB with no wait states
Figure 7-3 shows the available SRAM/cache configurations for L1D.
L1D mode bits
000
001
010
011
100
L1D memory
Block base
address
00F0 0000h
All
SRAM
7/8
SRAM
3/4
SRAM
1/2
SRAM
2-way
cache
2-way
cache
2-way
cache
2-way
cache
16KB
8KB
4KB
4KB
Figure 7-3. L1D Memory Configurations
00F0 4000h
00F0 6000h
00F0 7000h
00F0 8000h
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