1N4007 Datasheet, PDF (151/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.16 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU and send
synchronization events to the EDMA3 channel controller.
6.16.1 Timers Device-Specific Information
The C6654 and C6652 devices have seven 64-bit timers in total. Timer0 is dedicated to the CorePac as a
watchdog timer and can also be used as a general-purpose timer. Each of the other six timers can also be
configured as a general-purpose timer only, programmed as a 64-bit timer or as two separate 32-bit
timers.
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising
edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-
programmable period.
When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up
of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are
connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a
requirement that software writes to the timer before the count expires, after which the count begins again.
If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be
set by programming Section 6.6.2.6 and the type of reset initiated can set by programming
Section 6.6.2.8. For more information, see the 64-bit Timer (Timer 64) for KeyStone Devices User's Guide.
6.17 Semaphore2
The device contains an enhanced semaphore module for the management of shared resources of the
DSP C66x CorePac. The semaphore enforces atomic accesses to shared chip-level resources so that the
read-modify-write sequence is not broken. The semaphore module has a unique interrupt to the CorePac
to identify when the core has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software
requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.
The semaphore module supports 8 master and contains 32 semaphores to be used within the system.
The Semaphore module is accessible only by masters with privilege ID (privID) 0, which means only
CorePac 0 or the EDMA transactions initiated by CorePac 0 can access the Semaphore module.
There are two methods of accessing a semaphore resource:
• Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be
granted. If not, the semaphore is not granted.
• Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an
interrupt notifies the CPU that it is available.
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Detailed Description 151