1N4007 Datasheet, PDF (106/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.9 Interrupts
6.9.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6654 and C6652 devices are configured through the C66x CorePac Interrupt
Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the 12
CPU interrupt inputs (CPUINT4–CPUINT15), the CPU exception input (EXCEP), or the advanced
emulation logic. The 128 system events consist of both internally-generated events (within the CorePac)
and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are
not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. In
addition, error-class events or infrequently used events are also routed through the system event router to
offload the C66x CorePac interrupt selector. This is accomplished through CIC blocks, CIC[1:0]. This is
clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to the C66x
CorePacs, plus the EDMA3_CC and CIC0 provide 12 additional events as well as 8 broadcast events to
the C66x CorePacs. CIC1 provides 18 additional events to EDMA3_CC.
There are numerous events on the chip-level. The chip-level CIC provides a flexible way to combine and
remap those events. Multiple events can be combined to a single event through chip-level CIC. However,
an event can be mapped only to a single event output from the chip-level CIC. The chip-level CIC also
allows the software to trigger system events through memory writes. The broadcast events to C66x
CorePacs can be used for synchronization among multiple cores, interprocessor communication purposes,
and so forth. For more details on the CIC features, see the Chip Interrupt Controller (CIC) for KeyStone
Devices User's Guide.
NOTE
Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and an EOI
handshaking interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.
Figure 6-18 shows the C6654 and C6652 interrupt topology.
58 Reserved Secondary Events
92 Core-only Secondary Events
58 Common Events
CIC0
16 Reserved Secondary Events
102 Primary Events
12 Secondary Events
6 Reserved Primary Events
Core0
8 Broadcast Events from CIC0
58 Common Events
11 Reserved Secondary Events
56 Reserved Secondary Events
46 EDMA3_CC-only
Secondary Events
CIC1
40 Primary Events
18 Secondary Events
6 Reserved Primary Events
Figure 6-18. C6654 and C6652 Interrupt Topology
EDMA3
CC
106 Detailed Description
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