1N4007 Datasheet, PDF (82/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
OFFSET
0xA58
0xA5C
0xA60
0xA5C - 0xFFC
REGISTER
MDCTL22
MDCTL23
MDCTL24
Reserved
Table 6-7. PSC Register Memory Map (continued)
DESCRIPTION
Module Control Register 22(Reserved)
Module Control Register 23(C66x CorePac 0 and Timer 0)
Timer1
Reserved
6.5 Reset Controller
The reset controller detects the different type of resets supported on the C6654 and C6652 devices and
manages the distribution of those resets throughout the device.
The device has several types of resets:
• Power-on reset
• Hard reset
• Soft reset
• CPU local reset
Table 6-8 explains further the types of reset, the reset initiator, and the effects of each reset on the device.
For more information on the effects of each reset on the PLL controllers and their clocks, see
Section 5.7.2.
Table 6-8. Reset Types
RESET TYPE
POR
(Power On Reset)
Hard reset
Soft reset
C66x CorePac
local reset
INITIATOR
EFFECT ON DEVICE WHEN RESET OCCURS
RESETSTAT
PIN STATUS
POR pin active low
RESETFULL pin active low
Total reset of the chip. Everything on the device is reset to its
default state in response to this. Activates the POR signal on
chip, which is used to reset test/EMU logic. Boot configurations
are latched. ROM boot process is initiated.
Toggles
RESETSTAT pin
RESET pin active low
Emulation
PLLCTL register (RSCTRL)
Watchdog timers
Resets everything except for test/EMU logic and reset isolation Toggles
modules. Emulator and reset Isolation modules stay alive during RESETSTAT pin
this reset. This reset is also different from POR in that the
PLLCTL assumes power and clocks are stable when device
reset is asserted. Boot configurations are not latched. ROM
boot process is initiated.
RESET pin active low
PLLCTL register (RSCTRL)
Watchdog timers
Software can program these initiators to be hard or soft. Hard
reset is the default, but can be programmed to be soft reset.
Soft reset will behave like hard reset except that EMIF16
MMRs, DDR3 EMIF MMRs, sticky bits in PCIe MMRs, and
external memory contents are retained. Boot configurations are
not latched. ROM boot process is initiated.
Toggles
RESETSTAT pin
MMR bit in LPSC controls C66x CorePac local reset. Used by
Software (through LPSC _{watchdog timers (in the event of a time-out) to reset C66x}
MMR) Watchdog timers
CorePac. Can also be initiated by LRESET device pin. C66x
LRESET pin
CorePac memory system and slave DMA port are still alive
when C66x CorePac is in local reset. Provides a local reset of
the C66x CorePac, without destroying clock alignment or
memory contents. Does not initiate ROM boot process.
Does not toggle
RESETSTAT pin
82
Detailed Description
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