1N4007 Datasheet, PDF (186/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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7.1.3 L2 Memory
The L2 memory configuration for the C6654 and C6652 devices is as follows:
• Total memory is 1024KB
• Each core contains 1024KB of memory
• Local starting address for each core is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The
amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2
Configuration Register (L2CFG) of the C66x CorePac. Figure 7-4 shows the available SRAM/cache
configurations for L2. By default, L2 is configured as all SRAM after device reset.
L2 Mode Bits
000
001
010
011
100
101
110
L2 Memory
Block Base
Address
0080 0000h
1/2
SRAM
ALL
SRAM
31/32
SRAM
15/16
SRAM
7/8
SRAM
3/4
SRAM
4-Way
Cache
512KB
0088 0000h
256KB
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
Figure 7-4. L2 Memory Configurations
128KB
64KB
32KB
32KB
008C 0000h
008E 0000h
008F 0000h
008F 8000h
008F FFFFh
186 C66x CorePac
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