1N4007 Datasheet, PDF (171/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.24.2.5 I²C Boot Device Configuration
6.24.2.5.1 I²C Master Mode
In master mode, the I²C device configuration uses 10 bits of device configuration instead of 7 as used in
other boot modes. In this mode, the device will make the initial read of the I²C EEPROM while the PLL is
in bypass mode. The initial read will contain the desired clock multiplier, which will be set up prior to any
subsequent reads. I²C master mode is shown in Figure 6-34 and described in Table 6-70.
Figure 6-34. I²C Master Mode Device Configuration Bit Fields
12
11
10
9
8
7
6
5
4
3
Mode
Address
Speed
Parameter Index
Table 6-70. I²C Master Mode Device Configuration Field Descriptions
Bit
Field
12
Mode
11 - 10 Address
9
Speed
8-3
Parameter Index
Description
I²C operation mode
• 0 = Master mode
• 1 = Passive mode (see Section 6.24.2.5.2)
I²C bus address configuration
• 0 = Boot from I²C EEPROM at I²C bus address 0x50
• 1 = Boot from I²C EEPROM at I²C bus address 0x51
• 2= Boot from I²C EEPROM at I²C bus address 0x52
• 3= Boot from I²C EEPROM at I²C bus address 0x53
I²C data rate configuration
• 0 = I²C slow mode. Initial data rate is SYSCLK / 5000 until PLLs and clocks are programmed
• 1 = I²C fast mode. Initial data rate is SYSCLK / 250 until PLLs and clocks are programmed
Identifies the index of the configuration table initially read from the I2C EEPROM
This value can range from 0 to 31.
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