1N4007 Datasheet, PDF (103/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.8.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode.
Constant addressing mode is applicable to a very limited set of use cases. For most applications,
increment mode must be used. On the C6654 and C6652, the EDMA can use constant addressing mode
only with the Enhanced Viterbi-Decoder Coprocessor (VCP) and the Enhanced Turbo Decoder
Coprocessor (TCP). Constant addressing mode is not supported by any other peripheral or internal
memory in the device. Increment mode is supported by all peripherals, including VCP and TCP. For more
information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3) for
KeyStone Devices User's Guide.
For the range of memory addresses that include EDMA3 channel controller (EDMA3_CC) control registers
and EDMA3 transfer controller (TC) control register, see Table 6-60. For memory offsets and other details
on EDMA3_CC and TC control registers entries, see the Enhanced Direct Memory Access 3 (EDMA3) for
KeyStone Devices User's Guide.
6.8.2 EDMA3 Channel Controller Configuration
Table 6-23 provides the configuration of the EDMA3 channel controller present on the device.
Table 6-23. EDMA3 Channel Controller Configuration
DESCRIPTION
Number of DMA channels in Channel Controller
Number of QDMA channels
Number of interrupt channels
Number of PaRAM set entries
Number of event queues
Number of Transfer Controllers
Memory Protection Existence
Number of Memory Protection and Shadow Regions
EDMA3_CC
64
8
64
512
4
4
Yes
8
6.8.3 EDMA3 Transfer Controller Configuration
Each transfer controller on a device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), and so on. The
parameters that determine the transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses, in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register set. The number of
destination FIFO register set for a transfer controller determines the maximum number of outstanding
transfer requests.
All four parameters listed above are specified by the design of the device.
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Detailed Description 103