1N4007 Datasheet, PDF (86/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.5.6 Reset Controller Register
The reset controller register is part of the PLLCTL MMRs. All C6654 and C6652 device-specific MMRs are
covered in Section 6.6.3. For more details on these registers and how to program them, see the Phase-
Locked Loop (PLL) for KeyStone Devices User's Guide.
6.6 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL controller. For details on the operation of
the PLL controller module, see the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide.
The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios,
alignment, and gating for the system clocks to the device. Figure 6-3 shows a block diagram of the main
PLL and the PLL controller.
CORECLK(N|P)
PLL
PLLD xPLLM /2
0
OUTPUT
DIVIDE
1
BYPASS
PLLOUT
PLL Controller
1
0
01
PLLEN 0
PLLENSRC
/1
PLLDIV1
/x
PLLDIV2
/2
PLLDIV3
/3
PLLDIV4
/y
PLLDIV5
/64
PLLDIV6
/6
PLLDIV7
/z
PLLDIV8
/12
PLLDIV9
/3
PLLDIV10
/6
PLLDIV11
SYSCLK1
SYSCLK2
C66x
CorePac
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
To Switch Fabric,
Peripherals,
Accelerators
SYSCLK8
SYSCLK9
SYSCLK10
SYSCLK11
Figure 6-3. Main PLL and PLL Controller
86
Detailed Description
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