C8051F02X Datasheet, PDF (96/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 11.2. Comparator Hysteresis Plot
CP0+
VIN+
VIN- ^CP0-
+
CP0
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
VIN+
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
to logic 0. Comparator0 can also be programmed as a reset source; for details, see Section “13.6. Comparator0
Reset” on page 129.
The operation of Comparator1 is identical to that of Comparator0, though Comparator1 may not be configured as a
reset source. Comparator1 is controlled by the CPT1CN Register (Figure 11.4). The complete electrical specifications
for the Comparators are given in Table 11.1.
96
Rev. 1.4