C8051F02X Datasheet, PDF (201/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
19.4. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Reg-
ister, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special
function registers related to the operation of the SPI0 Bus are described in the following section.
Figure 19.5. SPI0CFG: SPI0 Configuration Register
R/W
CKPHA
Bit7
R/W
CKPOL
Bit6
R
BC2
Bit5
R
BC1
Bit4
R
BC0
Bit3
R/W
SPIFRS2
Bit2
R/W
SPIFRS1
Bit1
R/W
SPIFRS0
Bit0
Reset Value
00000111
SFR Address:
0x9A
Bit7:
Bit6:
Bits5-3:
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
BC2-BC0: SPI0 Bit Count.
Indicates which of the up to 8 bits of the SPI0 word have been transmitted.
BC2-BC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
BIT Transmitted
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (MSB)
Bits2-0: SPIFRS2-SPIFRS0: SPI0 Frame Size.
These three bits determine the number of bits to shift in/out of the SPI0 shift register during a data
transfer in master mode. They are ignored in slave mode.
SPIFRS
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Bits Shifted
1
2
3
4
5
6
7
8
Rev. 1.4
201