C8051F02X Datasheet, PDF (181/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 17.23. P6: Port6 Data Register
R/W
P6.7
Bit7
R/W
P6.6
Bit6
R/W
P6.5
Bit5
R/W
P6.4
Bit4
R/W
P6.3
Bit3
R/W
P6.2
Bit2
R/W
P6.1
Bit1
R/W
P6.0
Bit0
Reset Value
11111111
SFR Address:
0x86
Bits7-0:
P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.
Note:
P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEM-
ORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External
Memory Interface.
Figure 17.24. P7: Port7 Data Register
R/W
P7.7
Bit7
R/W
P7.6
Bit6
R/W
P7.5
Bit5
R/W
P7.4
Bit4
R/W
P7.3
Bit3
R/W
P7.2
Bit2
R/W
P7.1
Bit1
R/W
P7.0
Bit0
Reset Value
11111111
SFR Address:
0x96
Bits7-0:
P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
Note:
P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or
as D[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEMORY INTER-
FACE AND ON-CHIP XRAM” on page 145 for more information about the External Memory
Interface.
Rev. 1.4
181