C8051F02X Datasheet, PDF (107/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
12.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two sepa-
rate memory spaces: program memory and data memory. Program and data memory share the same address space but
are accessed via different instruction types. There are 256 bytes of internal data memory and 64k bytes of internal
program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in
Figure 12.2.
Figure 12.2. Memory Map
PROGRAM/DATA MEMORY
(FLASH)
0x1007F
0x10000
0xFFFF
0xFE00
0xFDFF
Scrachpad Memory
(DATA only)
RESERVED
0xFF
0x80
0x7F
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
0x0000
0xFFFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-chip XRAM space
0x1000
0x0FFF
0x0000
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
12.2.1. Program Memory
The CIP-51 has a 64k byte program memory space. The MCU implements 65536 bytes of this program memory
space as in-system re-programmed FLASH memory, organized in a contiguous block from addresses 0x0000 to
0xFFFF. Note: 512 bytes (0xEE00 to 0xFFFF) of this memory are reserved for factory use and are not available for
user program storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting
the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism
for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Sec-
tion “15. FLASH MEMORY” on page 139 for further details.
Rev. 1.4
107