C8051F02X Datasheet, PDF (250/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
23.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the
16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H
into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register
first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb
the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 23.1. Note that in ‘External oscillator source divided by 8’ mode, the external oscillator source
is synchronized with the system clock, and must have a frequency less than or equal to the system clock.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be glo-
bally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7)
and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue
normal operation while the CPU is in Idle mode.
Table 23.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
0
0
0
System clock divided by 12
0
0
1
System clock divided by 4
0
1
0
Timer 0 overflow
0
1
1 _{High-to-low transitions on ECI}^‡ _{(max rate = system clock divided by 4)}
1
0
0
System clock
1
0
1
External oscillator source divided by 8^†
†_{External oscillator source divided by 8 is synchronized with the system clock.}
‡_{The minimum high or low time for the ECI input signal is at least 2 system clock cycles.}
Figure 23.2. PCA Counter/Timer Block Diagram
IDLE
PCA0MD
CWW
I DD
DT L
LEC
K
CCCE
PPPC
SSSF
210
PCA0CN
CC CCCCC
FR CCCCC
FFFFF
43210
SYSCLK/12
000
SYSCLK/4
001
Timer 0 Overflow
010
ECI
011
SYSCLK
100
External Clock/8
101
PCA0L
read
Snapshot
Register
To SFR Bus
0
PCA0H
PCA0L
Overflow
To PCA Interrupt System
1
CF
To PCA Modules
250
Rev. 1.4