English
Language : 

C8051F02X Datasheet, PDF (36/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family
C8051F020/1/2/3
Table 4.1. Pin Definitions
Pin Numbers
Name
F020 F021 Type Description
F022 F023
A14m/A6/P2.6 40 31 D I/O Port 2.6. See Port Input/Output section for complete description.
A15m/A7/P2.7 39 30 D I/O Port 2.7. See Port Input/Output section for complete description.
AD0/D0/P3.0 54 47 D I/O Bit 0 External Memory Address/Data bus (Multiplexed mode)
Bit 0 External Memory Data bus (Non-multiplexed mode)
Port 3.0
See Port Input/Output section for complete description.
AD1/D1/P3.1 53 46 D I/O Port 3.1. See Port Input/Output section for complete description.
AD2/D2/P3.2 52 45 D I/O Port 3.2. See Port Input/Output section for complete description.
AD3/D3/P3.3 51 44 D I/O Port 3.3. See Port Input/Output section for complete description.
AD4/D4/P3.4 50 43 D I/O Port 3.4. See Port Input/Output section for complete description.
AD5/D5/P3.5 49 42 D I/O Port 3.5. See Port Input/Output section for complete description.
AD6/D6/P3.6/IE6 48 39 D I/O Port 3.6. See Port Input/Output section for complete description.
AD7/D7/P3.7/IE7 47 38 D I/O Port 3.7. See Port Input/Output section for complete description.
P4.0
98
D I/O Port 4.0. See Port Input/Output section for complete description.
P4.1
97
D I/O Port 4.1. See Port Input/Output section for complete description.
P4.2
96
D I/O Port 4.2. See Port Input/Output section for complete description.
P4.3
95
D I/O Port 4.3. See Port Input/Output section for complete description.
P4.4
94
D I/O Port 4.4. See Port Input/Output section for complete description.
ALE/P4.5
93
D I/O ALE Strobe for External Memory Address bus (multiplexed mode)
Port 4.5
See Port Input/Output section for complete description.
/RD/P4.6
92
D I/O /RD Strobe for External Memory Address bus
Port 4.6
See Port Input/Output section for complete description.
/WR/P4.7
91
D I/O /WR Strobe for External Memory Address bus
Port 4.7
See Port Input/Output section for complete description.
A8/P5.0
88
D I/O Bit 8 External Memory Address bus (Non-multiplexed mode)
Port 5.0
See Port Input/Output section for complete description.
A9/P5.1
87
D I/O Port 5.1. See Port Input/Output section for complete description.
A10/P5.2
86
D I/O Port 5.2. See Port Input/Output section for complete description.
36
Rev. 1.4