C8051F02X Datasheet, PDF (30/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
1.9. Comparators and DACs
Each C8051F020/1/2/3 MCU has two 12-bit DACs and two comparators on chip. The MCU data and control inter-
face to each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator
in low power shutdown mode.
The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising
edge, falling edge, or both; these interrupts are capable of waking up the MCU from sleep mode. The comparators'
output state can also be polled in software. The comparator outputs can be programmed to appear on the Port I/O pins
via the Crossbar.
The DACs are voltage output mode, and include a flexible output scheduling mechanism. This scheduling mecha-
nism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The DAC voltage
reference is supplied via the dedicated VREFD input pin on C8051F020/2 devices or via the internal voltage refer-
ence on C8051F021/3 devices. The DACs are especially useful as references for the comparators or offsets for the
differential inputs of the ADC.
Figure 1.13. Comparator and DAC Diagram
(Port I/O)
(Port I/O)
CP0
CP1
CROSSBAR
CP0+
CP0-
+
CP0
-
CP1+
CP1-
DAC0
+
CP1
-
REF
DAC0
CP0
CP1 ^SFR's
(Data
and
Cntrl)
CIP-51
and
Interrupt
Handler
DAC1
REF
DAC1
30
Rev. 1.4