C8051F02X Datasheet, PDF (159/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Table 16.1. AC Parameters for External Memory Interface
PARAMETER
DESCRIPTION
T_SYSCLK
System Clock Period
T_ACS
Address / Control Setup Time
T_ACW
Address / Control Pulse Width
T_ACH
Address / Control Hold Time
T_ALEH
Address Latch Enable High Time
T_ALEL
Address Latch Enable Low Time
T_WDS
Write Data Setup Time
T_WDH
Write Data Hold Time
T_RDS
Read Data Setup Time
T_RDH
Read Data Hold Time
MIN
40
0
1*T_SYSCLK
0
1*T_SYSCLK
1*T_SYSCLK
1*T_SYSCLK
0
20
0
MAX
UNITS
ns
3*T_SYSCLK
ns
16*T_SYSCLK ns
3*T_SYSCLK
ns
4*T_SYSCLK
ns
4*T_SYSCLK
ns
19*T_SYSCLK ns
3*T_SYSCLK
ns
ns
ns
Rev. 1.4
159