C8051F02X Datasheet, PDF (258/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
23.2.6. 16-Bit Pulse Width Modulator Mode
Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module
defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module
contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM Mode is
enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle,
CCFn should also be set to logic 1 to enable match interrupts. The duty cycle for 16-Bit PWM Mode is given by
Equation 23.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare
registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to
PCA0CPHn sets ECOMn to ‘1’
Equation 23.3. 16-Bit PWM Duty Cycle
DutyCycle = ⁽---6---5---5---3---6----–-----^P----^C----^A----0----^C----^P----ⁿ----⁾
65536
Using Equation 23.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is 0.0015%
(PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
1 0000 0
Figure 23.9. PCA 16-Bit PWM Mode
PCA0CPHn PCA0CPLn
Enable
16-bit Comparator
match _S SET _Q
CEXn _Crossbar
PCA Timebase
PCA0H
PCA0L
Overflow
RQ
CLR
Port I/O
258
Rev. 1.4