C8051F02X Datasheet, PDF (173/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 17.10. P0: Port0 Data Register
R/W
P0.7
Bit7
R/W
P0.6
Bit6
R/W
P0.5
Bit5
R/W
P0.4
Bit4
R/W
P0.3
Bit3
R/W
P0.2
Bit2
R/W
P0.1
Bit1
R/W
Reset Value
P0.0 11111111
Bit0 SFR Address:
(bit addressable) 0x80
Bits7-0:
P0.[7:0]: Port0 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory Interface.
See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on
page 145 for more information. See also Figure 17.9 for information about configuring the Crossbar
for External Memory accesses.
Figure 17.11. P0MDOUT: Port0 Output Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA4
Bits7-0: P0MDOUT.[7:0]: Port0 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
Note:
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
Rev. 1.4
173