C8051F02X Datasheet, PDF (237/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.1.3. Mode 2: Baud Rate Generator
Timer 2 can be used as a baud rate generator for UART0 when UART0 is operated in modes 1 or 3 (refer to Section
“20.1. UART0 Operational Modes” on page 206 for more information on the UART0 operational modes). In Baud
Rate Generator mode, Timer 2 works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two
capture registers (RCAP2H, RCAP2L) is automatically loaded into the counter/timer register. However, the TF2
overflow flag is not set and no interrupt is generated. Instead, the overflow event is used as the input to the UART's
shift clock. Timer 2 overflows can be selected to generate baud rates for transmit and/or receive independently.
The Baud Rate Generator mode is selected by setting RCLK0 (T2CON.5) and/or TCLK0 (T2CON.2) to ‘1’. When
RCLK0 or TCLK0 is set to logic 1, Timer 2 operates in the auto-reload mode regardless of the state of the CP/RL2
bit. Note that in Baud Rate Generator mode, the Timer 2 timebase is the system clock divided by two. When selected
as the UART0 baud clock source, Timer 2 defines the UART0 baud rate as follows:
Baud Rate = SYSCLK / ((65536 - [RCAP2H, RCAP2L] ) * 32)
If a different time base is required, setting the C/T2 bit to logic 1 will allow the timebase to be derived from the exter-
nal input pin T2. In this case, the baud rate for the UART is calculated as:
Baud Rate = F_CLK / ( (65536 - [RCAP2H, RCAP2L] ) * 16)
Where F_CLK is the frequency of the signal (TCLK) supplied to Timer 2 and [RCAP2H, RCAP2L] is the 16-bit value
held in the capture registers.
As explained above, in Baud Rate Generator mode, Timer 2 does not set the TF2 overflow flag and therefore cannot
generate an interrupt. However, if EXEN2 is set to logic 1, a high-to-low transition on the T2EX input pin will set the
EXF2 flag and a Timer 2 interrupt will occur if enabled. Therefore, the T2EX input may be used as an additional
external interrupt source.
Figure 22.13. T2 Mode 2 Block Diagram
C/T2
SYSCLK
2
0
T2
Crossbar 1
TCLK
TL2
RCLK0
Timer 2
Overflow
TH2
0
TR2
PCON
SS SS S I
MS MS TD
OT OT OL
DA DA PE
0T 1T
01
Reload
RCAP2L RCAP2H
16
1
0
Timer 1
Overflow
2
0
1
T2EX
EXEN2
Crossbar
CP/RL2
C/T2
TR2
EXEN2
TCLK0
RCLK0
EXF2
TF2
Interrupt
16
1
TCLK0
RX0 Clock
TX0 Clock
Rev. 1.4
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