C8051F02X Datasheet, PDF (240/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.2. Timer 3
Timer 3 is a 16-bit timer formed by the two 8-bit SFRs, TMR3L (low byte) and TMR3H (high byte). Timer 3 may be
clocked by the external oscillator source (divided by eight) or the system clock (divided by either one or twelve as
specified by the Timer 3 Clock Select bit T3M in the Timer 3 Control Register TMR3CN). Timer 3 is always config-
ured as an auto-reload timer, with the reload value held in the TMR3RLL (low byte) and TMR3RLH (high byte) reg-
isters.
The Timer 3 external clock source feature offers a real-time clock (RTC) mode. When bit T3XCLK (TMR3CN.0) is
set to logic 1, Timer 3 is clocked by the external oscillator input (divided by 8) regardless of the system clock selec-
tion. This split clock domain allows Timer 3 to be clocked by a precision external source while the system clock is
derived from the high-speed internal oscillator. When T3XCLK is logic 0, the Timer 3 clock source is specified by bit
T3M (TMR3CN.1).
Timer 3 can also be used to start an ADC Data Conversion, for SMBus timing (see Section “18. SYSTEM MAN-
AGEMENT BUS / I2C BUS (SMBUS0)” on page 183), or as a general-purpose timer. Timer 3 does not have a
counter mode.
External
Oscillator Source
SYSCLK
Figure 22.19. Timer 3 Block Diagram
8
12
0
1
T3XCLK
1
0
TR3
TCLK ^{TMR3L TMR3H}
T3M
(from SMBus) TOE
SCL Crossbar
Reload _{TMR3RLL TMR3RLH}
(to ADC)
TF3
Interrupt
TR3
T3M
T3XCLK
240
Rev. 1.4