C8051F02X Datasheet, PDF (33/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
4. PINOUT AND PACKAGE DEFINITIONS
Table 4.1. Pin Definitions
Name
VDD
DGND
AV+
AGND
TMS
TCK
TDI
TDO
/RST
XTAL1
XTAL2
MONEN
VREF
VREFA
VREF0
VREF1
VREFD
Pin Numbers
F020 F021 Type Description
F022 F023
37, 64, 24, 41,
90 57
Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
38, 63, 25, 40,
89 56
Digital Ground. Must be tied to Ground.
11, 14 6
Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
10, 13 5
Analog Ground. Must be tied to Ground.
1
58 D In JTAG Test Mode Select with internal pull-up.
2
59 D In JTAG Test Clock with internal pull-up.
3
60 D In JTAG Test Data Input with internal pull-up. TDI is latched on the
rising edge of TCK.
4
61 D Out JTAG Test Data Output with internal pull-up. Data is shifted out on
TDO on the falling edge of TCK. TDO output is a tri-state driver.
5
62 D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven
low when VDD is <2.7 V and MONEN is high. An external source
can initiate a system reset by driving this pin low.
26 17 A In Crystal Input. This pin is the return for the internal oscillator circuit
for a crystal or ceramic resonator. For a precision internal clock,
connect a crystal or ceramic resonator from XTAL1 to XTAL2. If
overdriven by an external CMOS clock, this becomes the system
clock.
27 18 A Out Crystal Output. This pin is the excitation driver for a crystal or
ceramic resonator.
28 19 D In VDD Monitor Enable. When tied high, this pin enables the internal
VDD monitor, which forces a system reset when VDD is < 2.7 V.
When tied low, the internal VDD monitor is disabled.
12
7 A I/O Bandgap Voltage Reference Output (all devices).
DAC Voltage Reference Input (F021/3 only).
8 A In ADC0 and ADC1 Voltage Reference Input.
16
A In ADC0 Voltage Reference Input.
17
A In ADC1 Voltage Reference Input.
15
A In DAC Voltage Reference Input.
Rev. 1.4
33