C8051F02X Datasheet, PDF (208/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
20.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data
bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications and
hardware address recognition (see Section “20.2. Multiprocessor Communications” on page 210). On transmit,
the ninth data bit is determined by the value in TB80 (SCON0.3). It can be assigned the value of the parity flag P in
the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and
the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt
Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met:
1. SM20 is logic 0
2. SM20 is logic 1, the received 9th bit is logic 1, and the received address matches the UART0 address as
described in Section 20.2.
If the above conditions are satisfied, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set.
An interrupt will occur if enabled when either TI0 or RI0 is set.
The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, depending on the value of the SMOD0 bit in regis-
ter PCON.
Equation 20.3. Mode 2 Baud Rate
BaudRate
=
2^SMOD0
×


S_----Y_----S_-6--C_-4---L_----K_{--}
MARK
SPACE
BIT TIMES
START
BIT
BIT SAMPLING
Figure 20.5. UART Modes 2 and 3 Timing Diagram
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
208
Rev. 1.4