C8051F02X Datasheet, PDF (260/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 23.11. PCA0MD: PCA0 Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CIDL
-
CPS2
CPS1
CPS0
ECF 01000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xD9
Bit7:
Bits6-4:
Bits3-1:
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
UNUSED. Read = 000b, Write = don't care.
CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
CPS2 CPS1 CPS0 Timebase
0
0
0
System clock divided by 12
0
0
1
System clock divided by 4
0
1
0
Timer 0 overflow
0
1
1
High-to-low transitions on ECI^†
(max rate = system clock divided by 4)
1
0
0
System clock
1
0
1
External clock divided by 8^‡
1
1
0
Reserved
1
1
1
Reserved
† _{The minimum high or low time for the ECI input signal is at least 2 system clock cycles.}
‡ _{External oscillator source divided by 8 is synchronized with the system clock.}
Bit0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
260
Rev. 1.4