C8051F02X Datasheet, PDF (163/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
17.1. Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to the digital
peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port pins are allocated in
order starting with P0.0 and continue through P3.7 if necessary. The digital peripherals are assigned Port pins in a pri-
ority order which is listed in Figure 17.3, with UART0 having the highest priority and CNVSTR having the lowest
priority.
17.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in
the Crossbar configuration registers XBR0, XBR1, and XBR2, shown in Figure 17.7, Figure 17.8, and Figure 17.9.
For example, if the UART0EN bit (XBR0.2) is set to a logic 1, the TX0 and RX0 pins will be mapped to P0.0 and
P0.1 respectively. Because UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when
UART0EN is set to a logic 1. If a digital peripheral’s enable bits are not set to a logic 1, then its ports are not accessi-
ble at the Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when a serial
communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to assign TX0
Figure 17.3. Priority Crossbar Decode Table
(EMIFLE = 0; P1MDIN = 0xFF)
P0
P1
P2
P3
Crossbar Register Bits
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
●
RX0
●
UART0EN: XBR0.2
SCK
●●
MISO
MOSI
●●
●●
SPI0EN: XBR0.1
NSS
●●
SDA
●●●●
SCL
●●●●
SMB0EN: XBR0.0
TX1
●●●●●
RX1
● ● ● ●●●
UART1EN: XBR2.2
CEX0 _{● ● ● ● ● ● ●}
CEX1
● ● ● ●●●●●
CEX2
● ● ● ●●●●●
PCA0ME: XBR0.[5:3]
CEX3
● ● ●●●●●●●
CEX4
● ● ●●●●●●●
ECI
●●●●●●●●●●●●●●●●
ECI0E: XBR0.6
CP0
●●●●●●●●●●●●●●●●●
CP0E: XBR0.7
CP1
●●●●●●●●●●●●●●●●●●
CP1E: XBR1.0
T0
●●●●●●●●●●●●●●●●●●●
T0E: XBR1.1
/INT0 _{● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●}
INT0E: XBR1.2
T1
●●●●●●●●●●●●●●●●●●●●●
T1E: XBR1.3
/INT1 _{● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●}
INT1E: XBR1.4
T2
●●●●●●●●●●●●●●●●●●●●●●●
T2E: XBR1.5
T2EX _{● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●}
T2EXE: XBR1.6
T4
●●●●●●●●●●●●●●●●●●●●●●●●●
T4E: XBR2.3
T4EX _{● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●}
T4EXE: XBR2.4
/SYSCLK ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●
SYSCKE: XBR1.7
CNVSTR _{● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●}
CNVSTE: XBR2.0
AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Muxed Data/Non-muxed Data
Rev. 1.4
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